Cmos device with dual polycide gates and method of manufacturing the same

ABSTRACT

A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well and the p+ polycide gate at the N-well are formed. An interlayer dielectric layer is formed on the resultant of the silicon substrate having the n+ polycide gate and the p+ polycide gate. A first bit-line contact hole for exposing the n+ polycide gate is formed, and a second bit-line contact hole for exposing the p+ polycide gate is formed. Bit-lines with a bridge structure on the interlayer dielectric layer is formed. The bit-lines simultaneously contact the n+ polycide gate and the p+ polycide gate through the first and second bit-line contact holes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a CMOS device and a method ofmanufacturing the same, and more particularly to a CMOS device with dualpolycide gates and a method of manufacturing the same, which is capableof stabilizing gate characteristic of peripheral circuit region.

2. Description of the Prior Art

As well known in the art, a gate of a MOS device has been primarily madefrom polysilicon. This is because the polysilicon has proper physicalcharacteristics for a gate, such as a high melting point, facilitationof thin film formation, facilitation of a line pattern, stabilizationfor an oxide atmosphere, and flat surface formation. Further, in thecase where the polysilicon is actually applied to MOSFET device, thegate made from the polysilicon implies dopant such as Phosphorus,Arsenic, Boron, etc. and achieves a low resistance.

However, with increasing integration of MOS devices, the line widths andresistance of gates should decrease. In order to achieve low resistancein the fine lines having the narrow width in highly integrated devices,research has been actively undertaken in pursuit of a transitional metalpolycide gate, which will have the structure in which a transitionalmetal-silicide, such as tungsten silicide, titanium silicide, nickelsilicide and the like, and polysilicon are stacked instead of anexisting polysilicon gate. Especially, the tungsten silicide of thetransitional polycides can realize a low resistance on a fine wirewidth, and satisfies characteristics required as the gate. Thus, thetungsten silicide is expected to have a use in manufacturing largeintegrated devices.

On the other hand, CMOS device has n+ polysilicon gate formed in all ofNMOS and PMOS regions. In this case, there is a problem in that a buriedchannel is formed by a counter-doping in the PMOS region, which therebyincreases a short channel effect.

As an attempt to solve the problem above problem, a method of forming adual gate has recently been used, in which n+ polysilicon gate is formedin NMOS region and p+ polysilicon gate is formed in PMOS region. Thedual gate forming method solves the problem due to the buried channel byforming surface channels in both the NMOS and PMOS regions.

Further, a technology for forming dual polycides, which includes a dualgate forming technology and a polycide gate forming technology graftedtogether, has been proposed. In order to realize a gate in a highlyintegrated device having low resistance as well as being able torestrict the short channel effect, the technology for forming dualpolycides is necessary.

Hereinafter, a method of manufacturing CMOS device with dual polycidegates according to a conventional art will be described in brief withreference to FIGS. 1A to 1D.

Referring to FIG. 1A, after a device isolation layer 2 is formed in asilicon substrate 1 to define an active region, masking process and ionimplant process as well-known are performed to form P-well 3 a andN-well 3 b on the silicon substrate 1. Then, a gate oxide layer 4 and apolysilicon layer 5 are sequentially formed on the silicon substrate 1on which the device isolation layer 2 and the wells 3 a and 3 b.

Referring to FIG. 1B, the masking and ion implantation processes areperformed by known methods to form n+ polysilicon layer 5 a and p+polysilicon layer 5 b in the P-well 3 a and the N-well 3 b,respectively.

Referring to FIG. 1C, a metal silicide layer 6 and a hard mask layer 7are sequentially formed on polysilicon layers 5 a and 5 b of whichregions are differently doped.

Next, though not shown in detail herewithin, after the hard mask layer 7is patterned to define the gate region, the metal silicide layer 6, thedoped polysilicon layers 5 a and 5 b, and the gate oxide layer 4 belowthe patterned hard mask 7 are sequentially etched by using the patternedhard mask 7 as an etching barrier, thereby forming the dual polycidegate including n+ polycide gate 10 a for NMOS and p+ polycide gate 10 bfor PMOS.

Referring to FIG. 1D, an insulating interlayer 8 is formed on theresultant to cover the dual polycide gate. Then, after the insulatinginterlayer 8 and the hard mask layer 7 are etched to form a bit linecontact hole 9, a bit-line 15 contacting the metal silicide layer of thedual polycide gates 10 a, 10 b is formed on the insulating interlayer 8.

FIG. 1E is a plan view showing a CMOS device manufactured by the methodof FIG. 1D, where FIG. 1D is a cross-sectional view taken along the lineA-A′ in FIG. 1E. As shown in FIG. 1E, the dual polycide gate 10, i.e.continuous word-lines are transversely arranged, while the bit-lines 15are longitudinally arranged perpendicularly to the word-lines. Thebit-line 15 contacts the corresponding one of the word-lines at the“contact” point as shown FIG. 1E, which more exactly is at the boundarybetween the NMOS and PMOS.

In the conventional method of forming dual polycide gate as describedabove, however, a dopant inter-diffusion may likely occur between theNMOS and PMOS in the peripheral circuit region.

Specifically, since the n+ polysilicon layer 5 a of the NMOS and the p+polysilicon layer 5 b of PMOS are adjacent to each other in theperipheral circuit region, n type impurity and p type impurity doped inthe n+ polysilicon layer 5 a and p+ polysilicon layer 5 b, respectively,are inter-diffused through the metal silicide layer, so as to cause acounter-doping effect in each gate polysilicon layer in an annealingprocess for a formation of the interlayer dielectric layer and asucceeding process. Thus, a serious gate depletion effect occurs, inwhich a sufficient concentration of impurities in each gate polysiliconlayer quickly decreases. As a result, the electrical characteristics ofthe device will degrade (e.g. the threshold voltage changes). Evenworse, it may cause a transistor to lose its on/off operationalcapability.

In addition, the distance between devices in the peripheral circuitregion has decreased in the highly integrated semiconductor devices.Therefore, the likelihood of dopant inter-diffusion between the gate ofthe NMOS and the gate of the PMOS increase as the devices are furtherhighly integrated. It is expected that the gate depletion effect will bemore serious due to this dopant inter-diffusion.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been developed in order to solvethe above-mentioned problems occurring in the prior art, and an objectof the present invention is to provide a CMOS device and a method ofmanufacturing the same, which can prevent a dopant inter-diffusionbetween gates of an NMOS and a PMOS in a peripheral circuit region.

Another object of the present invention is to provide a CMOS device anda method of manufacturing the same, which can stabilize gatecharacteristics in a peripheral circuit region.

Still another object of the present invention is to provide a CMOSdevice and a method of manufacturing the same, which can stabilize gatecharacteristics so as to improve a device characteristic.

In order to accomplish these objects of the present invention, accordingto an aspect of the present invention, there is provided a CMOS devicewhich comprises: a silicon substrate divided into a cell area and aperipheral circuit area, and having a device isolation layer, a P-well,and a N-well in the peripheral circuit area; n+ polycide gate formed inP-well region of the peripheral circuit area of the substrate, and p+polycide gate formed in N-well region of the peripheral circuit area ofthe substrate so as to be separated from the n+ polycide gate; aninterlayer dielectric layer formed on a resultant of the siliconsubstrate having the n+ polycide gate and the p+ polycide gate, andincluding a first bit-line contact hole for exposing the n+ polycidegate and a second bit-line contact hole for exposing the p+ polycidegate; and bit-lines formed on the interlayer dielectric layer to have abridge structure, and simultaneously contacting with the n+ polycidegate and the p+ polycide gate which are separated from each other,through the first and second bit-line contact holes.

Here, the n+ polycide gate is formed with a stack layer including a gateinsulation layer, a silicon layer in which n-type impurity is implanted,a metal silicide layer, and a hard mask layer, while the p+ polycidegate is formed with a stack layer including the gate insulation layer, asilicon layer in which p-type impurity is implanted, the metal silicidelayer, and the hard mask layer.

The bit-lines are formed to contact with each metal silicide layer ofthe n+ polycide gate and the p+ polycide gate.

In order to accomplish these objects of the present invention, accordingto another aspect of the present invention, there is provided a methodof manufacturing a CMOS device which has dual polycide gate, whichcomprises the steps of: providing a silicon substrate which is dividedinto a cell area and a peripheral circuit area and has a deviceisolation layer, a P-well, and a N-well in the peripheral circuit area;forming the n+ polycide gate at the P-well in the peripheral circuitarea of the substrate and the p+ polycide gate at the N-well in theperipheral circuit area of the substrate so as to be separated from then+ polycide gate, the n+ polycide gate being formed with a stack layerincluding a gate being formed with a stack layer including a gateinsulation layer, a silicon layer in which n-type impurity is implanted,a metal silicide layer, and a hard mask layer, while the p+ polycidegate is formed with a stack layer including the gate insulation layer, asilicon layer in which p-type impurity is implanted, the metal silicidelayer, and the hard mask layer; forming an interlayer dielectric layeron a resultant of the silicon substrate having the n+ polycide gate andthe p+ polycide gate; forming a first bit-line contact hole for exposingthe n+ polycide gate and a second bit-line contact hole for exposing thep+ polycide gate; and forming bit-lines with a bridge structure on theinterlayer dielectric layer, the bit-lines simultaneously contactingwith the n+ polycide gate and the p+ polycide gate, which are separatedfrom each other, through the first and second bit-line contact holes.

According to another aspect of the present invention, the step offorming the n+ polycide gate and the p+ polycide gate comprises thesub-steps of: forming a gate insulation layer and a silicon layer in thesubstrate, sequentially; selectively ion-implanting n-type impurity in aportion of the silicon layer formed at the P-well region in theperipheral area of the substrate, while selectively ion-implantingp-type impurity in a portion of the silicon layer formed at the N-wellregion in the peripheral area of the substrate; sequentially forming themetal silicide layer and the hard mask layer on the silicon layer ofeach region in which the n-type and p-type impurities are ion-implanted;and etching the hard mask layer, the metal silicide layer, the siliconlayer, and the gate insulation layer.

The silicon layer is formed in an armorphos state.

The n-type impurity ion implant is performed by using Phosphorus orArsenic, while the p-type impurity ion implant is performed by usingBoron or Boron difluoride.

The metal silicide layer is formed with a tungsten silicide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features, and advantages of the presentinvention will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIGS. 1A to 1D are cross-sectional views for illustrating a method ofmanufacturing a CMOS device according to a conventional art, in whichprocesses are shown step by step; and

FIG. 1E is a plan view showing a CMOS device manufactured by the processof FIG. 1D, where FIG. 1D is a cross-sectional view taken along the lineA-A′ in FIG. 1E;

FIGS. 2A to 2D are cross-sectional view for illustrating a method ofmanufacturing a CMOS device according to an embodiment of the presentinvention; and

FIG. 2E is a plan view showing a CMOS device manufactured by the processof FIG. 2E according to an embodiment of present invention, where FIG.2D is a cross-sectional view taken along the line B-B′ in FIG. 2E.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention will bedescribed with reference to the accompanying drawings.

FIGS. 2A to 2D are cross-sectional views for illustrating a method ofmanufacturing a CMOS device according to an embodiment of the presentinvention, in which processes are shown step by step.

Referring to FIG. 2A, a device isolation layer 22 is formed to define anactive region in each area of a silicon substrate 21 having a cell areaand a peripheral circuit area, according to a shallow trench isolationprocess, and in turn an existing mask process and ion implantationprocess are performed, so as to form a P-well 23 a and a N-well 23 b inthe peripheral circuit area of the silicon substrate 21. Thereafter, anoxide layer 24 is formed as a gate insulation layer on the siliconsubstrate 21 on which the device isolation layer 22, and wells 23 a and23 b are formed, and then a silicon layer 25 for a gate is formed on theoxide layer 24.

Here, the oxide layer 24 is formed at a thickness of 20˜60 Å accordingto a wet oxidation process. Further, the oxide layer 24 may have aoxynitride layer formed by nitrifying a surface of the oxide layer inorder to restrain boron from penetrating in the oxide layer 24 during asubsequent ion implantation process. An amorphous silicon layer ispreferably used as the silicon layer 25 for the gate, but if necessary,a polysilicon layer instead of the amorphous silicon layer can be usedas the silicon layer 25 for the gate.

Referring to FIG. 2B, n-type impurity is selectively ion-implanted onthe silicon layer 25 in the P-well 23 a region of the peripheral circuitarea of the substrate, so as to form the n+ silicon layer 25 a, whilep-type impurity is selectively ion-implanted on the silicon layer 25 inthe N-well region 23 a of the peripheral circuit area of the substrate,so as to form the p+ silicon layer 25 b. Here, the n-type of impurityion implantation is carried out using Phosphorus or Arsenic, while the ptype impurity ion implantation is carried out using Boron or Borondifluoride.

Referring to FIG. 2C, a metal silicide layer 26, such as a tungstensilicide layer, and a hard mask layer 27 are sequentially formed on thesilicon layers 25 a and 25 b in which different conductive-impuritiesare implanted. Then, the hard mask layer 27 is patterned. The patterningof the hard mask layer 27 is carried out in order to form adiscontinuous gate (word-line) in which the gate of NMOS and the gate ofPMOS are divided.

Next, the metal silicide layer 26, the silicon layer 25 a and 25 b, andthe oxide layer 24 which are below the patterned hard mask 27, aresequentially etched by using the patterned hard mask 27 as an etchingbarrier. At a result, n+ polycide gate 30 a is formed on the P-well 23 aof the peripheral circuit area of the substrate, while p+ polycide gate30 b are formed on the N-well 23 b of the peripheral circuit area of thesubstrate so as to be separated from the n+ polycide gate 30 a. That is,unlike the prior art example, the n+ silicon layer 25 a and the p+silicon layer 25 b are separated by the above etching process as shownin FIG. 1C.

According to an embodiment of the present invention, here, the n+polycide gate 30 a of NMOS and the p+ polycide gate 30 b of PMOS areseparated from each other as described above, and the separationprevents dopant inter-diffusion between the n+ polycide gate 30 a ofNMOS and the p+ polycide gate 30 b of PMOS. Thus, it is possible toprevent the gate depletion effect caused by dopant inter-diffusion.

Referring to FIG. 2D, the interlayer dielectric layer 28 is formed on aresultant of the silicon substrate to cover the n+ polycide gate 30 a ofthe NMOS and the p+ polycide gate 30 b of the PMOS, and then theinterlayer dielectric layer 28 and the hard mask layer 27 areselectively etched, so as to form the first and second bit-line contactholes 29 a and 29 b exposing the metal silicide layer 26 of the n+polycide gate 30 a and the metal silicide layer 26 of the p+ polycidegate 30 b. Next, the conductive substance, such as tungsten, isdeposited in order to bury the first and second bit-line contact holes29 a and 29 b in the interlayer dielectric layer 28, and then thedeposited layer is patterned, so as to form a bit-line 35 having abridge structure and contacting with the n+ polycide gate 30 a and thep+ polycide gate 30 b.

FIG. 2E is a plan view of a CMOS device manufactured according to anembodiment of the present invention as shown in FIG. 2D, where FIG. 2Dis a cross-sectional view taken along the line B-B′ of FIG. 2E. As shownin FIG. 2D, the dual polycide gates including n+ polycide gate 30 a andp+ polycide gate 30 b, i.e. the word-lines are discontinuously formed ineach of the NMOS region and the PMOS region, respectively, while thebit-lines 35 have the structure in which the contacts, i.e. bit-linecontacts formed at two points at which the bit-lines 35 contact the n+polycide gate 30 a and the p+ polycide gate 30 b, are bridged to connectthe separated n+ and p+ polycide gates 30 a and 30 b to each other.

In the conventional art, the word-line is continuous and there is only abit-line contact region. In the present invention, however, theword-lines are discontinuous and electrically connected to each other bythe bit-lines 35. Thus, the present invention can realize a CMOS devicein which the dopant inter-diffusion between the n+ polycide gate of NMOSand the p+ polycide gate of PMOS and the gate depletion effect caused bythe dopant inter-diffusion can be effectively prevented.

Thereafter, well-known processes are successively performed in order toaccomplish the semiconductor device of the present invention not shown.

As described above, in the method of manufacturing the CMOS devicehaving dual gates in the peripheral circuit area, the n+ polycide gateand p+ polycide gate are formed in the N-well and P-well regions,respectively, and then the bit-line is formed to contact with the n+polycide gate and the p+ polycide gate, thereby fundamentally preventingthe dopant inter-diffusion between the NMOS and the PMOS.

Accordingly, the present invention can reduce an electric characteristicof the device, such as a threshold voltage characteristic, andeffectively restrain the gate depletion effect causing the malfunctionof the transistor. As a result, the reliability and yield of the devicecan be improved.

Furthermore, since the present invention can solve the gate depletioneffect of the peripheral circuit area, which is a critical problem intechnology used in a manufacture of CMOS device having the dual polycidegates in order to realize a very large scale of integrated device, thereis an advantage in that it is capable of being profitably applied to amanufacture of a next generation of the very large scale of integrateddevice.

While a preferred embodiment of the present invention has been describedfor illustrative purposes, those skilled in the art will appreciate thatvarious modifications, additions and substitutions are possible, withoutdeparting from the scope and spirit of the invention as disclosed in theaccompanying claims.

1. A method of manufacturing a CMOS device having a dual polycide gate structure, the method comprising the steps of: providing a silicon substrate, which is divided into a cell area and a peripheral circuit area, having a device isolation layer between a P-well region and a N-well region in the peripheral circuit area; forming a n+ polycide gate having at least a first metal silicide layer at the P-well region and a p+ polycide gate having at least a second metal silicide layer at the N-well region, wherein the n+ polysilicon gate and the p+ polysilicon gate are separated from each other; forming an interlayer dielectric layer on the n+ polycide gate and on the p+ polycide gate and on the substrate between the separated n+ and p+ polycide gates; forming a first bit-line contact hole for exposing the n+ polycide gate through the interlayer dielectric layer and a second bit-line contact hole for exposing the p+ polycide gate through the interlayer dielectric layer; and forming a bit-line having a first end and a second end formed on the interlayer dielectric layer, wherein the first end is connected to the n+ polycide gate and the second end is connected to the p+ polycide gate such that a bridge structure is formed on the interlayer dielectric layer, the bit-lines simultaneously contacting with the n+ polycide gate and the p+ polycide gate, which are separated from each other, through the first and second bit-line contact holes.
 2. The method of claim 1, wherein the step of forming the n+ polycide gate and the p+ polycide gate comprises the sub-steps of: forming a gate insulation layer and a silicon layer on the substrate, sequentially; selectively ion-implanting n-type impurity in a portion of the silicon layer formed at the P-well region in the peripheral area of the substrate, while selectively ion-implanting p-type impurity in a portion of the silicon layer formed at the N-well region in the peripheral area of the substrate; sequentially forming the metal silicide layer and the hard mask layer on the silicon layer of each region in which the n-type and p-type impurities are ion-implanted; and etching the hard mask layer, the metal silicide layer, the silicon layer, and the gate insulation layer, wherein the portion of the metal silicide layer formed on the P-well region is the first metal silicide layer and the portion of the metal silicide layer formed on the N-well region is the second metal silicide layer.
 3. The method of manufacturing a CMOS device as claimed in claim 2, wherein the silicon layer is formed in an armorphos state.
 4. The method of manufacturing a CMOS device as claimed in claim 2, wherein the n-type impurity ion implant is performed by using Phosphorus or Arsenic.
 5. The method of manufacturing a CMOS device as claimed in claim 2, wherein the p-type impurity ion implant is performed by using Boron or Boron difluoride.
 6. The method of manufacturing a CMOS device as claimed in claim 1, wherein the metal silicide layer is formed with a tungsten silicide layer. 